janick.bergeron.com
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Writing Testbenches
Using SystemVerilog

I have recently completed a new version of my book on how to write testbenches using SystemVerilog. It describes the techniques that I have developed during my career as a Design Verification Engineer. Click on the book cover on the left for more details.

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Writing Testbenches
Functional Verification of HDL Models

This is the second edition of my book on how to write testbenches using e, OpenVera, Verilog or VHDL. It describes the techniques that I have developed during my career as a Design Verification Engineer. Click on the book cover on the left for more details.

Click here for more details.

Verification Guild
A Community of Practice the verification professional
  The Verification Guild is a moderated mailing list where verification professionals can discuss any issues and challenges presented by this most difficult task.

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Earlier Work
  Top-Down Design Using VHDL

A tutorial originally presented at the Fall VIUF conference in 1993. Click here for a copy of the slides and source code (367k).

Some personal stuff
  I am shamelessly taking advantage of my webpage's good ranking with Google to link to my personal pages/websites and thus improve their rankings.