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 Functional Verification of HDL Models |
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New for 2006!
Writing Testbenches Using SystemVerilog The popular Writing Testbenches book is now available with a 100% SystemVerilog content. Click here for more details. |
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The second edition of Writing Testbenches: Functional Verification of HDL Models builds on the acclaimed content and approach of the first edition to introduce new advancements in functional verification using High-Level Verification Languages (HVLs). The second edition continues to avoid language details in favor of methodology and applications. New in the second edition...
Readers are saying... "Required reading by anyone involved in design and verification of today's ASICs, SoCs, and systems" "Clearly outlines the necessary steps to verify the complex functionality of modern hardware design" More... "Clearly describes recent advancements in functional verification" More... "Brilliant" More... "continues to keeps pace with the industry while providing world-class solution to the verification problem" More... "If there can ever be such a thing as a 'classic book' in the EDA field, then this is most certainly a candidate for that honor" More... "A must have bible for understanding verification issues and techniques with HDLs and HVLs" More... |
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From the back cover | ||
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Verification now consumes over 70% of the effort to design an ASIC. |
Verification is often approached in an ad hoc fashion, without planning, and without taking full advantage of the power of available languages. Visually inspecting simulation results is no longer feasible. The directed testcase methodology is reaching its limit. FPGAs can no longer be debugged in the lab and require ASIC-like functional verification methodologies. Moore's Law demands a productivity revolution in functional verification methodology. | ||
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Plan and implement a strategy for first- time success. |
Writing Testbenches: Functional Verification of HDL Model offers a clear blueprint of a verification process that aims for first-time success. From simulators to source management tools, from specification to functional coverage, from 1's and 0's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all. | ||
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What readers said about the 1st edition...
"This is one of the best written books in my shelf. Highly recommended." More... "we (...) finally have a book focusing on streamlining and improving the verification process" More... "Probably one of the best HDL books out there, period" More... "A seminal work for hardware designers. (...) the BEST (book) I have purchased by far." More... "Well worth the price" More... "I love the book" More... "It gave me the roots I need to perform my responsibilities effectively" More... "An excellent guide for any engineer to effectively know the importance of HDL in verification" More... "A well thought out and well written book" More... "A very excellent (and needed) work!" More... "A very good achievement (...) in one of the least understood areas of hardware design" More... "I strongly recommend it" More... "Clear, thorough, and very reflective of the real-world" More... "The first to address the part that matters most" More... "This book is a must have for every design verification person" More... "Read and re-read chapters 1-3 before ever learning a line of Verilog or VHDL syntax" More... "The bible for writing testbenches" More...
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