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 Functional Verification of HDL Models |
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| Home | | | Contents | | | Reviews | | | Errata | | | Resources | | | Guild | | | Source | ||
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Reviews of the 2nd edition |
| If you wish to write a review, simply send it via email to janick@bergeron.com. | |
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Janick Bergeron clearly outlines the necessary steps to verify the
functionality of modern hardware designs. At every step he shows in
great detail the many available alternatives such as linting tools,
simulators, code coverage, bus functional models, and more. His
knowledge of verification is encyclopedic.
The second edition addresses the problem that testbenches in Verilog and VHDL can no longer keep up with the complexity of the designs. Janick clearly explains concepts such as constrained randomization, functional coverage, and object oriented programming, and how they can help verification engineers meet the challenges as projects grow more complicated. |
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- Chris Spear, Verification Specialist Synopsys, Inc. |
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| Clearly describes recent advancements in functional verification, such as coverage-driven constrained random generation using hardware verification languages. | |
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- Andrew Piziali, Verification Consultant Verisity Design. |
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| Read Grant's review of the 1st edition | Brilliant. Janick Bergeron has built on his ground-breaking first version of Writing Testbenches in this second edition, deeply embedding the key additional topics of Hardware Verification Languages, and coverage-driven random-based verification. I look forward to the third edition, which will no doubt add a discussion of the SystemC verification library capabilities and extend the treatment to full C++-based verification methods |
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- Grant Martin, Fellow Cadence Berkeley Labs |
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In the latest edition, Mr. Bergeron continues to keeps pace with the
industry while providing world-class solution to the verification
problem. His latest edition embraces the verification paradigm shift
to HVLs and explains how to use them to achieve higher confidence in a
design in less time.
Mr. Bergeron not only explains how to verify today's complex designs, but also walks through the entire design process - from selecting the proper tools and creating a verification plan, to knowing when the verification effort is (finally) finished. |
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- Chris Macionski, Senior Engineer Qualis Design Corp. |
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| When I first heard about this book, I had a healthy amount of skepticism based on the superficial nature in which most books tend to treat verification - lots of details about file IO, PLI etc. and a great deal of hand waving when it comes to the important issues. But this book is different in that it was the first book that truly is about verification and nothing else. It does not avoid the issues, but tackles them head on. If there can ever be such a thing as a 'classic book' in the EDA field, then this is most certainly a candidate for that honor. Many companies out there now owe their current verification methodologies to this book. From it they have learned the secrets of efficiency, effectiveness and re-use as they apply to verification, and have made their own efforts that much more valuable to their companies | |
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- Brian Bailey, Chief Technologist Mentor Graphics Corp. |
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| A must have bible for understanding verification issues and techniques with HDLs and HVLs, and for writing effective, readable and reusable testbenches within a best-in-class verification process. | |
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- Ben Cohen, VhdlCohen Training author of "VHDL Coding Styles and Methodologies", "VHDL Answers to Frequently Asked Questions" and "Component Design by Example". |
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