Reviews of the 1st edition

Reader reviews at:

I have your book. It is my bible for me when I am designing test benches. It has information I cannot find anywhere else. Thank you for sharing your knowledge.

- Jeffery A. Smith, Senior Development Engineer
Vanteon

I have been working in this industry for the past 8 years but I did not see any book for verification except it might be only one chapter in a book. This book gives me a formal and structural view of verification and its methodology. The excellence of this book is the key technical terms in verification are given as heading in the left hand side of every page. Hence I can call this book an encyclopedia for verification. Another fantastic aspect of this book is that it is not intended only for student, new designer or experienced designer but as a book for everybody. I believe that one who has gone through this book has no need to have a verification expert consultant for his/her project. You can save thousands of dollars from paying for a verification consultant. I appriciate Janick Bergeron for his best work.

- Kandaswamy Prabakaran, VLSI Design Engineer
Agere Systems Inc.

From a posting in a USENET newsgroup:

I started to do a 5206e model but the project got put on the back burner. I did something similar with this Cypress VMEbus chip set I used. I'd send you that model if it wasn't an embarrassing mess. (I bought a copy of Janick Bergeron's book and now I hate all of my testbenches!)

See Janick Bergeron's book, "Writing Testbenches -- Functional Verification of HDL Models" for some excellent information. Well worth the $98 Fatbrain.com charged for it.

- Andy Peters, Sr. Hardware Engineer
Synergy Microsystems, Inc.

I love the book (and the verification guild mailing list).

Excellent book. Is language neutral. Useful for anyone doing VHDL/Verilog design, not just testbench writers.

- Jeremy Nichols, Hardware engineer
Front end processes and tools, Unisys Corp.

I am a verification engineer and I just started my new position as of last month. I am trying to learn as much as I can about the verification methodology & broaden my knowledge in this arena.

I liked your book 'Writing Testbenches - Functional Verification of HDL models'. It gave me the roots I need to perform my responsibilities effectively.

- Farhan Mansoor,
Cirrus Logic, VLSI Design Engineering Dept.

I am a guy working basically on behavioural models, testcases and RTL level abstraction in a company called V3Logic in Bangalore, India.

Your book on verification "Writing Testbenches" is an excellent guide for any engineer to effectively know the importance of HDL in verification as this is what the present community of complex chip designers looks for.

- Mohan Kamraj, Senior Design Engineer
V3 Logic, Bangalore, India

I've just finished reading your book "Writing Testbenches" (twice in two days) and I congratulate you on a well thought out and well written book; as your reviews state, it fills a much needed gap in the technical literature on the subject that is often overlooked.

- Gareth Edwards, Design Engineer
Xilinx

I just finished reading your book, "Writing Testbenches". A very excellent (and needed) work! As an experienced verification engineer, I expecially appreciated your words about revision control and code maintainability.

One suggestion for future additions: I think it would be useful to discuss testbenches which aren't limited to HDL. You mentioned Verisity's e language briefly, but really didn't talk about the pluses or minuses. I've also used testbenches in which tests were written in C, perl, or Tcl, and communicated with Verilog via PLI.

- Bob Wood

Overall a good read, with an excellent view of the verification process. It's a very good achievement to get work of this quality in one of the least understood areas of hardware design.

Tackling the verification process in one book is a huge task but Bergeron has done extremely well here. He clarifies the process and it's dynamics very well. It's the type of book that I wish I had when entering the verification arena so now - there's no excuse.

For me it's the verification bible and I would recommend it to anyone. Even if you consider you're a designer this book will help you to interface most effectively to the verification process.

- David Murray, Chief Technologist
Inoru

When I saw your book mentioned in EETimes, I think, I immediately jumped to your web site to look in more detail, and after examining the Table of Contents, quickly ordered it. I think it's the first edition.

I'm slowly going through it, a couple of pages whevever I have a little free time.

So far I think it's great. As a long time verification engineer, I was very impressed by Chapter 1. The only comment I have is on pp 12-13, I would add that each of the 3 approaches, black-box, white-box, and grey-box, has limitations on the completeness of the verification it does. For example, black-box ignores details of implementation which need to be verified but which are not reflected in spec of design. Thus, all 3 approaches are needed and complementary.

- Shalom Bresticker,
Motorola Semiconductor Israel

I strongly recommend it. I don't agree with everything Janick says, and the coverage of certain critical topics is weak, but nevertheless, this is a very solid text and a must read for those in the verification game.

- Michael Thompson, Senior ASIC Design Engineer
MOSAID Technologies Inc.

I bought it at DesignCon in Santa Clara last week. I was actually surprised to finally see a book dedicated to the testbench/verification topic. I was definitely aware that this is the first book out of its kind. In fact, I wished that a book like this was around a couple years ago when I first started out in this field :) But still, the book is great to have now. I find it clear, thorough, and very reflective of the real-world.

Although I have acquired a lot of the knowledge in your book already through industry experience as an ASIC verification engineer, I still find it as a great reference and would refer it to anyone interested in understanding what an ASIC verification engineer does and their challenges. I personally feel that most engineers know their coding skills but having an effective verification methodology build with good techniques are the most challenging. Well, thanks again for writing this book.

- Brian Salim, Senior ASIC Design Engineer

I just wanted to drop you a quick email telling you how much I enjoyed my first read of your "Writing Testbenches". Self taught in VHDL, I have a dozen VHDL books on my shelf, and yours is the first to address the part that matters most! Designing large ASICs and FPGAs, we have moved from patching simulators together with named pipes, to finally a VHDL-pure testbench approach; and your text really clears up a lot of the rough bits we knew, but had not written down anywhere.

- Shepard Siegel, Principal Design Engineer
Datacube Inc.

""Writing Testbenches" is an encyclopedic collection of techniques to effectively verify hardware designs. (...) Extremely well organized, (...) the book is laid out to serve the experienced, junior and student audiences. (...) This book is a must have for every design verification person."

- Mike McNamara, Senior Vice-President of Technology
Verisity Design.

Read Grant's review of the 2nd edition!

"An overwhelmingly pragmatic focus. (...) The structure of the book, with the annotated paragraphs and a very logical flow, makes it an admirable textbook. (...) Students (...) [should] READ and RE-READ your chapters 1-3 BEFORE ever learning a line of Verilog or VHDL syntax. "

- Grant Martin, Senior Architect
System Level Design, Cadence Design Systems
co-author of " Surviving the SoC Revolution:
A Guide to Platform-Based Design ".

"You have written a very readable, and timely book that is going to become THE text to read for writing code to verify circuits."

- Himanshu Thaker, Broadband ASIC Engineer
Lucent Technologies Inc.

"The bible for techniques in writing effective, readable and reusable Verilog and VHDL testbenches within a best-in-class verification process"

- Ben Cohen, VhdlCohen Training
author of " VHDL Coding Styles and Methodologies"
and " VHDL Answers to Frequently Asked Questions".