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 Functional Verification of HDL Models |
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Table of Contents |
About the CoverForewordPreface
What This Book Is About What Prior Knowledge You Should Have Reading Paths Choosing a Language For More Information Acknowledgements CHAPTER 1: What is Verification?
The Importance of Verification Reconvergence Model The Human Factor
Poka-Yoke Redundancy
Equivalence Checking Model Checking Functional Verification
White-Box Verification Grey-Box Verification
Design for Verification
Verification for Reuse Verification Reuse Summary CHAPTER 2: Verification Tools
Linting Verilog Source Code Linting VHDL Source Code Linting OpenVera and e Source Code Code Reviews
Event-Driven Simulation Cycle-Based Simulation Co-Simulators
Code Coverage
Path Coverage Expression Coverage FSM Coverage What Does 100% Code Coverage Mean?
Cross Coverage Transition Coverage What Does 100% Functional Coverage Mean? Assertions
Formal Assertion Proving
Configuration Management Working with Releases
The Grapevine System The Post-It System The Procedural System Computerized System
Quality-Related Metrics Interpreting Metrics CHAPTER 3: The Verification Plan
Defining First-Time Success
Reusable Components Verification ASIC and FPGA Verification System-Level Verification Board-Level Verification
System-Level Features Error Types to Look For Prioritize Design for Verification
From Testcases to Testbenches Verifying Testbenches Measuring Progress
From Features to Functional Coverage From Features to Testbench From Features to Generators Directed Testcases CHAPTER 4: High-Level Modeling
Optimize the Right Thing Good Comments Improve Maintainability
Encapsulating Useful Subprograms Encapsulating Bus-Functional Models
Variant Records Arrays Lists Files Mapping High-Level Data Types to Physical Interface
Inheritance Polymorphism Limitations of OpenVera and e's OOP Implementation
Variant Data with Variant Code Limitations of e's AOP Implementation
Connectivity, Time and Concurrency in HDLs and HVLs The Problems with Concurrency Emulating Parallelism on a Sequential Processor The Simulation Cycle The Co-Simulation Cycle Parallel vs. Sequential Fork/Join Statement The Difference Between Driving and Assigning
Write/Write Race Conditions Initialization Races Guidelines for Avoiding Race Conditions Semaphores
Disabled Scheduled Values Output Arguments on Disabled Tasks Non-Re-Entrant Tasks CHAPTER 5: Stimulus and Response
Aligning Signals in Delta-Time Clock Multipliers Asynchronous Reference Signals Random Generation of Reference Signal Parameters Applying Reset
Encapsulating Waveform Generation Abstracting Waveform Generation
Producing Simulation Results Minimizing Sampling Visual Inspection of Waveforms Self-Checking Testbenches Input and Output Vectors Golden Vectors Self-Checking Operations
Recovering from Deadlocks Asynchronous Interfaces
From Bus-Functional Procedures to Bus-Functional Model OpenVera's Interface Model Bus-Functional Models in OpenVera Asynchronous Signals in OpenVera Synchronous Bus-Functional Models in e Asynchronous Bus-Functional Models in e Configurable Bus-Functional Models
Slave Generators Multiple Possible Transactions
Split Transactions Retries and Completion Status Symbol-Level Control CHAPTER 6: Architecting Testbenches
VHDL Test Harness
Abstracting the Client/Server Protocol Test Harness Multiple Server Instances
Configuring the Design Random Design Configuration
Data Tagging Reference Models Transfer Function Scoreboarding Integration with the Transaction Layer Random Stimulus
Adding Constraints in e Adding Constraints in OpenVera Constraining Sequences Defining Scenarios in OpenVera Defining Scenarios in e CHAPTER 7: Simulation Management
Example of Behavioral Modeling Characteristics of a Behavioral Model Modeling Reset Writing Good Behavioral Models Behavioral Models Are Faster The Cost of Behavioral Models The Benefits of Behavioral Models Demonstrating Equivalence Managing Simulations
Verilog Configuration Management VHDL Configuration Management OpenVera Configuration Management e Configuration Management SDF Back-Annotation Output File Management Seed Management
Regression Management APPENDIX A: Coding Guidelines
Verilog Specific
Layout Syntax Debugging
Identifiers Constants HDL & HVL Specific Filenames
Layout VHDL Specific Verilog Specific APPENDIX B: GlossaryAfterwordsIndex |