|
 Using SystemVerilog |
|
||||||||||||||
| Home | | | Contents | | | Reviews | | | Ask | | | Errata | | | Resources | | | Guild | | | Order | ||
|
|
Table of Contents |
About the CoverPreface
What This Book Is About What Prior Knowledge You Should Have Reading Paths Why Systemverilog? Code Examples For More Information Acknowledgements CHAPTER 1: What is Verification?
The Importance of Verification Reconvergence Model The Human Factor
Poka-Yoke Redundancy
Model Checking Functional Verification
White-Box Verification Grey-Box Verification
Design for Verification
Verification for Reuse Verification Reuse Summary CHAPTER 2: Verification Technologies
Linting SystemVerilog Source Code Code Reviews
Event-Driven Simulation Cycle-Based Simulation Co-Simulators Waveform Viewers Code Coverage
Path Coverage Expression Coverage FSM Coverage What Does 100% Code Coverage Mean?
Cross Coverage Transition Coverage What Does 100% Functional Coverage Mean? Assertions
Formal Assertion Proving
Configuration Management Working with Releases
The Grapevine System The Post-It System The Procedural System Computerized System
Quality-Related Metrics Interpreting Metrics CHAPTER 3: The Verification Plan
Defining First-Time Success
Block and Core Verification ASIC and FPGA Verification System-Level Verification Board-Level Verification
System-Level Features Error Types to Look For Prioritize Design for Verification
From Testcases to Testbenches Verifying Testbenches Measuring Progress
From Features to Functional Coverage From Features to Testbench From Features to Generators Directed Testcases CHAPTER 4: High-Level Modeling
Optimize the Right Thing Good Comments Improve Maintainability
Encapsulating Useful Subprograms Encapsulating Bus-Functional Models
Struct, Class Union Arrays Queues Associative Arrays Files From High-Level to Physical-Level
Inheritance Polymorphism
The Problems with Concurrency Emulating Parallelism on a Sequential Processor The Simulation Cycle The Co-Simulation Cycle Parallel vs. Sequential Fork/Join Statement The Difference Between Driving and Assigning
Write/Write Race Conditions Initialization Races Guidelines for Avoiding Race Conditions Semaphores
Disabled Scheduled Values Output Arguments on Disabled Tasks Non-Re-Entrant Tasks Static vs. Automatic variables CHAPTER 5: Stimulus and Response
Aligning Signals in Delta-Time Clock Multipliers Asynchronous Reference Signals Random Generation of Reference Signal Parameters Applying Reset
Abstracting Waveform Generation
Producing Simulation Results Minimizing Sampling Visual Inspection of Waveforms Self-Checking Testbenches Input and Output Vectors Golden Vectors Self-Checking Operations
Recovering from Deadlocks Asynchronous Interfaces
From Bus-Functional Tasks to Bus-Functional Model Physical Interfaces Configurable Bus-Functional Models
Slave Generators Multiple Possible Transactions
What is a Transaction? Blocking Transactions Nonblocking Transactions Split Transactions Exceptions CHAPTER 6: Architecting Testbenches
Design Configuration
Configuring the Design Random Design Configuration
Data Tagging Reference Models Transfer Function Scoreboarding Integration with the Transaction Layer Random Stimulus
Adding Constraints Constraining Sequences Defining Random Scenarios Defining Procedural Scenarios
CHAPTER 7: Simulation Management
Example of Transaction-Level Modeling Characteristics of a Transaction-Level Model Modeling Reset Writing Good Transaction-Level Models Transaction-Level Models Are Faster The Cost of Transaction-Level Models The Benefits of Transaction-Level Models Demonstrating Equivalence Managing Simulations
Avoiding Recompilation or SDF Re-Annotation Output File Management Seed Management
Regression Management APPENDIX A: Coding Guidelines
Layout Structure Debugging
Identifiers Constants APPENDIX B: GlossaryIndex |